1. Field of the Invention
The present invention relates to apparatus for testing VLSI circuit chips. In particular, the present invention is an improved built-in self-test system for VLSI circuit chips.
2. Description of the Prior Art
Very large-scale integrated (VLSI) circuit chips manufactured with modern integrated circuit (IC) technologies routinely hold over 10,000 devices (eg. transistors). VLSI circuits with 500,000 devices have been developed. The present trend in integrated circuit design is toward even higher levels of circuit integration, thereby reducing costs and improving circuit reliability. As IC technologies continue to develop, it is expected that circuits with at least 100,000,000 devices will become common.
Increased circuit integration is not, however, obtained without drawbacks. Increasing chip testing costs tend to reduce the benefits derived from more economically efficient design and production techniques. As discussed in an article entitled "Cutting Chip-Testing Costs," IEEE Spectrum, Volume 22, Number 4, April 1985, page 38, the costs associated with integrated circuit chip testing increase in proportion to the square of the number of devices thereon. Much expense is incurred in the development of computer programs for running test routines. The engineering effort and computer time needed to devise these test routines can even exceed the requirements for designing the chip itself. Depending upon the particular type of circuit involved, circuit chip testing costs now account for roughly 10 to 40 percent of the total manufacturing costs.
The most commonly used technique of IC testing is known as scan design. Scan design requires the circuit designer to break complex logic circuits into smaller blocks, and to include artificial pathways into and between the blocks for data transmission. Complex sequential circuitry is thereby temporarily converted to combinational circuitry for testing purposes.
Scan design techniques are far from optimal. Scan design does not, in general, permit faults to be isolated to a particular chip or wire net. The inclusion of additional test points and transmission paths required for scan design degrades overall IC performance. Scan design also requires additional clock circuitry and relatively complicated maintenance software.
Another testing technique, one that is becoming increasingly popular, is the built-in self-test technique. As its name implies, built-in self-test, or BIST, test systems are fabricated on the IC chip to be tested. BIST systems include a pattern or operand generator for producing test operands. Each test operand is applied to the IC logic, and the response thereto analyzed by means of a shift register. The response to thousands, and even millions, of test operands is then compressed into a "signature", which is compared to predetermined signatures for a go/no go indication of the IC's operation. One such BIST system is disclosed in the Van Brunt U.S. Pat. No. 4,357,703.
The BIST approach to circuit testing offers numerous advantages. BIST has minimal impact upon main logic functions since it is typically fabricated on the sparsely used peripheral areas of the integrated circuit chip. Since test results are processed by the BIST system, the number of tasks which must be performed by external test equipment is reduced. Specially developed maintenance software is therefore greatly reduced. Dynamic testing at full systme clock rates significantly reduces system test times. BIST systems can also be used for testing integrated circuits at the wafer, chip, and system levels. Since they are independent of specific chip logic functions, BIST test systems can be used on any number of different types of circuit chips. The BIST approach also permits IC chips to be tested after they have been assembled into a computer, even though they are inaccessible to more traditional maintenance techniques. This will be the case, for example, when the IC is immersed in a liquid coolant to increase its performance.
Even though they offer many advantages over alternative techniques, BIST test systems have yet to be developed to their full potential. BIST systems like that disclosed in U.S. Pat. No. 4,357,703 require the logic designer to carefully synchronize BIST test system control signals with the IC system clock. Only by accurately tuning these control signals can timing violations be avoided. Unless the logic designer pays careful attention to the logic state of the system clock, data held or stored within shift registers of this system will be lost. Although alternate test data from the main logic function could be outputted from this BIST test system, the logic designer was required to actively block the alternate test data when normal test data was being analyzed. In general, the BIST system disclosed in U.S. Pat. No. 4,357,703 constrained logic design.
There is clearly a continuing need for improved BIST systems. Controlability and observability are the goals. The logic designer should, for example, be able to use the BIST system to easily control and observe all operations on the integrated circuit. It would be especially desirable if timing constraints imposed upon the logic designer by the BIST system were eased, eliminating the need for accurate tuning of BIST system control signals with respect to the IC system clock. A BIST test system which maintains data held within its shift registers irrespective of system cock status would also be desirable. A BIST system which permits one of several different types of test data to be uniquely selected, without having to block those forms of test data not selected, is also needed. In general, all elements of the integrated circuit which are used for test operations should be under dedicated control of the BIST system.